From 405143faadc36ff92b11eaae1e1f36a16e4375c2 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Wed, 17 May 2017 02:23:22 +0200 Subject: [PATCH 06/27] spapr: Don't accidentally advertise HTM support on POWER9 RH-Author: David Gibson Message-id: <20170517022323.16930-2-dgibson@redhat.com> Patchwork-id: 75201 O-Subject: [Pegas-1.0 qemu-kvm-rhev PATCH 1/2] spapr: Don't accidentally advertise HTM support on POWER9 Bugzilla: 1449007 RH-Acked-by: Thomas Huth RH-Acked-by: Laurent Vivier RH-Acked-by: Laszlo Ersek From: David Gibson Logic in spapr_populate_pa_features() enables the bit advertising Hardware Transactional Memory (HTM) in the guest's device tree only when KVM advertises its availability with the KVM_CAP_PPC_HTM feature. However, this assumes that the HTM bit is off in the base template used for the device tree value. That is true for POWER8, but not for POWER9. It looks like that was accidentally changed in 9fb4541 "spapr: Enable ISA 3.0 MMU mode selection via CAS". Fixes: 9fb4541f5803f8d2ba116b12113386e26482ba30 Signed-off-by: David Gibson Reviewed-by: Thomas Huth (cherry picked from commit 9bf502fe127f04e393cacae9f2666e0c98c6df4f) Signed-off-by: David Gibson Signed-off-by: Miroslav Rezanina --- hw/ppc/spapr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index cc3ccc1..62e2696 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -247,7 +247,7 @@ static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, /* 16: Vector */ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ - 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ -- 1.8.3.1